1. Field of the Invention
The present invention relates to a voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device.
2. Description of Related Art
With development of portable electronic devices, demand for non-volatile memory is gradually increased. Since a phase change memory (PCM) technique has competitive characteristics of speed, power, capacity, reliability, process integration and cost, etc., it is regarded as a most promising next-generation non-volatile memory technique.
Regarding an operation of the PCM, two different currents are applied to the PCM, so that due to an ohm heating effect, different temperature variations of local regions of the PCM can cause a reversible phase transition of an amorphous state and a crystalline state of the phase change material, and such two phase change structures can present different resistances to achieve a purpose of storing data.
To convert the phase change material from the amorphous state to the crystalline state, an electrode of the PCM where the current is applied is suitably heated, so that the phase change material is heated to exceed a temperature to crystallize, and such operation is generally referred to as a SET operation. Similarly, to convert the phase change material from the crystalline state to the amorphous state, a current pulse is suitably applied to the PCM, so that the phase change material is heated to exceed a temperature to melt, and the amorphous state is obtained through a rapid cooling process. Such operation is generally referred to as a RESET operation. Based on the reversible phase transition of the amorphous state and the crystalline state of the phase change material, data storage can be achieved.
FIG. 1 is a schematic diagram illustrating current pulses used for writing and reading a PCM. When the RESET operation of the PCM is performed, a reset current IRESET with a short pulse width and a high pulse height is applied, so that a temperature of a local region of the PCM is higher than a melting temperature (Tm), and the local region is melted. When the melted local region is instantly cooled, since there is no enough time for re-crystallization, the amorphous state of the phase change material is formed during the cooling process, and now the phase change material has a high resistance. On the other hand, when the SET operation of the PCM is performed, a set current ISET with a wide pulse width and a low pulse height is applied, so that a temperature of the local region of the PCM is between a crystalline temperature (TC) and the melting temperature (Tm) of the phase change material, and the amorphous region can be recrystallized after the SET operation.
As described above, the RESET operation and the SET operation of the PCM are equivalent to a write operation and an erase operation of a memory, and a memory effect can be achieved based on a resistance variation generated by operating the PCM between the crystalline state to the amorphous state. When data of the PCM is read, a read current IREAD with a current value less than ISET is applied to determine the resistance, so as to obtain the stored data.
FIG. 2 is a schematic diagram illustrating a conventional SET signal of a PCM. The SET signal includes a first crystallization current pulse ISET1 and a second crystallization current pulse ISET2. The first crystallization current pulse ISET1 has a first current peak IP1, and a hold time of the first current peak IP1 is a first hold time t1. The second crystallization current pulse ISET2 has a second current peak IP2, and a hold time of the second current peak IP2 is a second hold time t2.
Regarding the conventional SET signal, a combination of two different current pulses is used to perform the SET operation. Under a pulse function of the higher first current peak IP1 with a shorter first hold time t1, a local region crystallization of the phase change material is first accomplished. Then, under a pulse function of the lower second current peak IP2 with a longer second hold time t2, a complete crystallization of the phase change material is achieved. According to such operation method of crystallization, a characteristic of stable reliability can be achieved, which also avails improving a uniformity of component distribution.
The aforementioned PCM has advantages of low power consumption, small area and fast operation speed, etc., and regarding a R-ratio of the PCM resistance, RESET is 10M-1M, and SET is 10K, so that R-ratio is 10M-1M/10K, which is closed to 1000-100 times, even reaches 1000 times. Since the R-ratio is great enough, in recent years, the world's major manufactures start to develop multi-level PCMs to replace flash memories. However, in recent published documents, when the PCM is not operated for a period of time, the high-impedance state resistance thereof is increased due to a long idle time, and such characteristic can cause a problem of read error for a multi-level and high-impedance state read operation. Therefore, a compensation mechanism is required to resolve the error in judgement.
A U.S. Patent No. 2008/0266942 provides a multi-level PCM device, in which an operation of pre-reading operation resistance drift recovery can be performed. As shown in FIG. 3A, to compensate the resistance drift, during a write operation, a compensation current ISense of a sensor amplifier circuit (SA) 310 and a recovery current IRecovery of a write driver (WD) 320 are used to perform the write operation to a bit line (BL) through an address selector 330, which is a write mechanism for compensating the resistance drift. As shown in FIG. 3B, the SA 310 is coupled to a phase change random access memory (PRAM) cell array 340 through the address selector 330 and the bit line. A circuit 350 provides a read current to the PRAM cell array 340, and obtains an output voltage to the SA 310 for determination. Therefore, during the write operation, the write current is compensated according to the resistance drift.
A U.S. Patent No. 2009/0016100 also provides a multi-level PCM device. Referring to FIG. 4A, the multi-level phase change memory device includes a main region 410 and a reference region 412 of a memory array region, a sensor amplifier circuit (shown as “SA” in FIG. 4A) 414, a reference voltage generator 416, a write driver (shown as “WD” in FIG. 4A) 418, an input/output buffer 420, a control circuit 422 and an address decoder 424.
As shown in FIG. 4, the reference voltage generator 416 generates a reference voltage Vref to the SA 414 for determination. A method that the reference voltage generator 416 generates the reference voltage Vref is shown as FIG. 4B and FIG. 4C. Original programmed states are 430, 432, 434 and 436, and drifted states are 431, 433, 435 and 437. Regarding reference voltages required by the multi-level PCM, voltages V1, V2, V3 and V4 of reference memory cells (RMC) are directly used to generate new reference voltages Vref1, Vref2, Vref3 and Vref4, and values of the reference voltages Vref1, Vref2 and Vref3 are respectively 1/2(V1+V2), 1/2(V2+V3), 1/2(V3+V4), which are provided to the SA 414 for determination.
Referring to FIG. 5, a U.S. Patent No. 2009/0003033 discloses a read method for a PCM. With respect to charge time of the bit line (shown as “BL” in FIG. 5), in different states, corresponding values of charged voltage of the BL and charge time are different, which has situations of 1-5 nanosecond (ns), and such method is not applied to a multi-level read operation and a compensation application thereof.
A U.S. Patent No. 2008/0316802 discloses a memory device having a drift compensation function and an operation method thereof. Referring to FIG. 6, when a memory array having the drift characteristics is read, a drift condition sensor system first performs a compensation detection, and then the reference voltage is modified according to a detected drift condition, as that shown in FIG. 6. However, in such patent, how to perform the compensation is not described, and a detail circuit thereof is not provided. Moreover, such patent is adapted to a read circuit having a compensation effect.